Most of today’s electronic products consist of traditional made parts. Plastic molded housings containing PCB’s with soldered THT and SMT components. In many cases even the design of a product is based on the electronics that should fit inside! Shouldn’t it be the other way around? Shouldn’t the electronics be a part of the design based on ergonomics and aesthetics?
The only way to establish this is by placing the electronics in some kind of way inside the design. This implements that the substrate on which the components should be place would be the inside of the designed housing itself. Since most housings are of a 3 dimensional shape the components might need to be placed under an angle, but more over the interconnections between the components can no longer be on a separate piece of FR4 material.
Also if we look on advanced 3D chip packaging level, interconnects are an important driver. This holds for Through Silicon Vias (TSVs) for chip stacking, but also for other interconnect steps like re-distribution layers and solder bumps. Especially in applications with a low number (<100 mm-2) of relatively large features (10-100 μm diameter) with high aspect ratio (up to 1:10), conventional plating processes are slow and become cumbersome with increasing aspect ratio, thus becoming cost ineffective. Hence, industrially feasible, alternative direct-write processes are of interest for advanced interconnects.
A general trend in IC manufacturing is that, driven by ever increasing performance and form factor requirements, chips become more and more integrated into very thin packages. Integration takes place on chip level, on silicon interposers and also by integrating ultra-thin chips into foil based devices.
Such integration requires new interconnect strategies like through-silicon vias (TSV’s), through-mould vias in wafer-level packages, redistribution layers for chip-scale ball grid arrays and all kinds of hybrid approaches to integrate thin silicon chips into foils or laminates. All these applications share the problem that existing industrial patterned metallization approaches are either costly or lack accuracy.
Traditionally, in IC manufacturing, a combination of sputtering and (electro)plating is the technology of choice. To create a pattern, the plating process always has to be combined with one or more lithographic masking and etching steps. Altogether, this combination of processing steps makes this a costly approach, especially when series are small. Further, novel packaging and interconnect approaches typically require metallization at enhanced aspect ratios e.g. in TSVs, which leads to an even stronger cost increase. At the same time, the total area coverage of the structures is often relatively small. Finally, novel packaging approaches are not always compatible with wet processing.
Direct-write technologies can form a low-cost alternative approach to create interconnects by eliminating mask and etch costs as well as by being more efficient at low area coverage and high aspect ratio.
All kind of techniques have already been developed to print interconnects. Existing direct write technologies to print interconnects are summarized in TABLE I. In most cases, either a metallic ink or paste (typically containing nano-particles) is used or an ink containing precursor for electroless plating. Metallic inks containing nanoparticles always require a thermal or photonic treatment to achieve sintering, hence electrical conductivity. Plating precursors need an (electro)less plating step to create the actual track. Hence, such precursor printing only solves part of the problems associated with the conventional approach.
In general, the approaches listed in Table I are well-established technologies (except for LIFT) and many amongst them are incorporated in industrial processes like printed circuit board production, solar cell production or electronics packaging. To be able to write structures compatibly with advanced IC packaging approaches, a deposition resolution of 1-5 μm is required. As can be seen from TABLE I, this is at least a factor of 10 smaller than most of the existing direct write figures. Only Laser Induced Forward Transfer is a technology that shows the potential to overcome this limitation.
|TABLE I Overview of existing direct write approaches|
|Method||Dimensions reported||Curing / plating required|
|Plasma Technology||200-2000 μm||No|
|Ink jet / micro-dispensing||20-100 μm||Yes|
|Aerosol jet (LENS)||10-50 μm||Yes|
|Laser Induced Forward Transfer (LIFT)||1-10 μm||No|
Laser Induced Forward Transfer (LIFT) is using a laser to shoot small droplets of conductive material from a carrier onto a substrate as shown in the below picture.
Note, that the deposition size is typically smaller than the hole in the donor layer. Further, the substrate and the donor both move with respect to the laser beam, each with their own velocity. This is needed in order to create overlapping deposits which form a conducting line.
Inkjet printing can be used in electronics packaging as interconnections between electronic components. Conductive inks and dielectric inks are used when substituting traditional printed circuit board (PCB) with inkjet-printed interconnections. Although both organic and inorganic inks can be used for conductive purposes, at the moment inorganic inks offer better conductivity. Inorganic ink consists of metal nanoparticles and organic solvent which make the ink printable.
Aerosol Jet Printing is another material deposition technology for printed electronics. The Aerosol Jet process begins with atomization of an ink, which can be heated up to 80°C, producing droplets on the order of one to two microns in diameter. The atomized droplets are entrained in a gas stream and delivered to the print head. Here, an annular flow of clean gas is introduced around the aerosol stream to focus the droplets into a tightly collimated beam of material. The combined gas streams exit the print head through a converging nozzle that compresses the aerosol stream to a diameter as small as 10microns.
The jet of droplets exits the print head at high velocity (~50 meters/second) and impinges upon the substrate. Electrical interconnects, passive and active components are formed by moving the print head, equipped with a mechanical stop/start shutter, relative to the substrate. The resulting patterns can have features ranging from 10 microns wide, with layer thicknesses from 10’s of nanometers to >10 microns. A wide nozzle print head enables efficient patterning of millimeter size electronic features and surface coating applications. All printing occurs without the use of vacuum or pressure chambers and at room temperature. The high exit velocity of the jet enables a relatively large separation between the print head and the substrate, typically 2-5mm. The droplets remain tightly focused over this distance, resulting in the ability to print conformal patterns over three dimensional substrates. Despite the high velocity, the printing process is gentle; substrate damage does not occur and there is generally no splatter or overspray from the droplets. Once patterning is complete, the printed ink typically requires post treatment to attain final electrical and mechanical properties.
3D MID technology (Moulded Interconnect Devices) is another way to create an electrical interconnect inside a moulded plastic housing. An electrical conductive circuit is created by means of two-shot moulding or by laser activation patterning. After this step the structures get metallized through an electroless plating process and become conductive. After the circuitry is created the conventional SMT machines (stencil printing, pick & place and reflow ovens) can make sure that components are added to the part.
Things can get even more interesting when we change our conventional way of thinking! What if we would first place the components inside the housing and secondly print the interconnects? In that case we do not need the reflow process either! It would however be beneficial to be able to print copper interconnects without a post treatment. Plasma technology could be a good option in this case. This kind of technology could revolutionize manufacturing processes for sensitive surfaces under atmospheric pressure. Cold active atmospheric plasma encompasses a multitude of applications in the industries like solar, semiconductors and could become a substitute technology for 3D MID. Plasma technology however still needs some extra attention to be able to create fine pitch tight tolerance interconnects.
What needs to be considered as well is the placement of the components. In case we create the electrical circuitry inside the housing and the shape is 3 dimensional, we need to be able to place components in a 3 dimensional way. This also implements that we need to be able to apply solder paste or glue in a 3 dimensional way as well. In case we could first place the components and afterwards print the conductive copper tracks, there might even be a need to change the design of certain components that have their connections or heat sinks on the bottom side.
What advantages can these changes bring the electronics industry? Besides the feature of having a product designed for purpose and not one to fit the electronics, there are some major cost saving advantages. In case the interconnects can be printed inside a housing, there is no more need for a printed circuit board. This is not only a cost saving advantage, but also an environmental advantage. Furthermore assembly steps of integrating the pcb into a housing is no longer needed which is another cost saving argument. If some of the components can be part of the printed interconnects than these components are no longer needed as conventional THT, or SMT component. In case we could first place components and secondly print the copper interconnects, no more solder paste needs to be applied and no reflow process is needed either. The solder paste however probably needs to be replaced by a gluing process to hold the components in place especially if components will be placed in a 3 dimensional way. Reducing production steps could implement faster production cycles. Especially in case this process could simplify a current complex sub-assembly, but for sure it will be a reduction of floor space and energy cost.
As you can see 3D Printing is not only focussed on the mechanical industry. There are several very interesting features that should be thoroughly investigated for the electronics industry as well. Pushing the technical limits and challenging the industry is the next step to be taken. TNO, a research institute in The Netherlands has started with a strategic research program on the topic of 3D printed electronics to develop new techniques and further develop existing techniques in close co-operation with the electronics industry and its partners. We expect that due to fast developments in 3D printing, the technology will mature in the coming years into a cost effective approach for electronics industry.